Automation of technological preparation of metal working on heavy machine tools

The programs for selection of the cutting tools construction and cutting regimes are working in unrestricted surroundings elaborate of addition SharpDevelop in language C#. By the appendix of Cosmos of the program SolidWorks the areas of plate break-age and tensions distributing arising up in it at the different values of cutting force are certain. Based on the conducted researches of durability the rational structural parameters of collapsible chisels, in particular, thickness of plate are grounded that provides the increase of efficiency of treatment of details a hard-alloy instrument on the heavy machine tool

An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration

In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e.g. in the well-known ImageNet challenge. As a result, great effort is being put into developing fast and efficient accelerators, especially for Convolutional Neural Networks (CNNs). In this work we present ConvAix, a fully C-programmable processor, which -- contrary to many existing architectures -- does not rely on a hard-wired array of multiply-and-accumulate (MAC) units. Instead it maps computations onto independent vector lanes making use of a carefully designed vector instruction set. The presented processor is targeted towards latency-sensitive applications and is capable of executing up to 192 MAC operations per cycle. ConvAix operates at a target clock frequency of 400 MHz in 28nm CMOS, thereby offering state-of-the-art performance with proper flexibility within its target domain. Simulation results for several 2D convolutional layers from well known CNNs (AlexNet, VGG-16) show an average ALU utilization of 72.5% using vector instructions with 16 bit fixed-point arithmetic. Compared to other well-known designs which are less flexible, ConvAix offers competitive energy efficiency of up to 497 GOP/s/W while even surpassing them in terms of area efficiency and processing speed.Comment: Accepted for publication in the proceedings of the 2019 IEEE International Symposium on Circuits and Systems (ISCAS

Методичні вказівки до семінарського заняття "Організаційні патології" з навчальної дисципліни "Основи управлінського консультування"

Методичні вказівки до проведення семінарського заняття з дисципліни "Основи управлінського консультування" тема "Організаційні патології" розроблено на допомогу у вивченні дисципліни та організації роботи студента на семінарських заняттях. Викладений матеріал орієнтує студентів на вивчення першоджерел та літератури, яка містить приклади практичного застосування досягнень науки менеджменту в діяльності вітчизняних компаній та компаній, які працюють у державах з ринковою економікою. У методичних вказівках наведені актуальні теми для підготовки до семінарського заняття на тему "Організаційні патології" за двома змістовними модулями: основні положення консультаційної діяльності; управління консалтинговою організацією

Programming MPSoC platforms: Road works ahead

This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. The current trend towards MPSoC platforms in most computing domains does not only mean a radical change in computer architecture. Even more important from a SW developer´s viewpoint, at the same time the classical sequential von Neumann programming model needs to be overcome. Efficient utilization of the MPSoC HW resources demands for radically new models and corresponding SW development tools, capable of exploiting the available parallelism and guaranteeing bug-free parallel SW. While several standards are established in the high-performance computing domain (e.g. OpenMP), it is clear that more innovations are required for successful\ud deployment of heterogeneous embedded MPSoC. On the other hand, at least for coming years, the freedom for disruptive programming technologies is limited by the huge amount of certified sequential code that demands for a more pragmatic, gradual tool and code replacement strategy

A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4x4 16-QAM system, the area increases by 57% and the operating frequency degrades by 34% only.Comment: Accepted for IEEE Transactions on Circuits and Systems II Express Briefs, May 2010. This draft from April 2010 will not be updated any more. Please refer to IEEE Xplore for the final version. *) The final publication will appear with the modified title "A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding

About interrelation of structure of an anomalous geochemical field with the mechanism of formation of hydrothermal system

The model of formation of anomalous structures of geochemical fields during formation of thermo-fluidic ore-forming system is proposed. The morphology of these fields is caused by the combination of diverged mineral zonation in relation to a power source and converging zonation in relation to the centers of an ore deposition. Influence of tectonic conditions of functioning of hydrothermal system on an internal structure of anomalous geochemical fields is shown. Connection of efficiency of hydrothermal deposits with structure of a geochemical field containing them is grounded